1. Field of the Invention
The invention relates in general to a multi-core electronic system, and more particularly to a technique for adjusting a data transmission rate of a multi-core system.
2. Description of the Related Art
Power consumption of a circuit increases as an operating frequency of the circuit increases, and therefore many circuits adopt different clock rates for accommodating different operating situations, so as to achieve power saving. Taking a central processor of a computer system for example, a processor 10 generally communicates with a storage unit 14 via a data transmission interface 12, as shown in FIG. 1. Apart from data, the processor 10 also sends control signals, e.g., clock rates for controlling a transmission rate of the data transmission interface 12 to the storage unit 14.
When the processor 10 is in a normal operation mode, the processor 10 may set the data transmission interface 12 to a medium rate for transmitting data. When no operations are to be handled, the processor 10 may then command the data transmission interface to operate at a lower frequency to reduce power consumption. On the contrary, when the processor 10 is required to read a large amount of data from the storage unit 14 (e.g., when handling video playback procedures) or write a large amount of data to the memory 14, the processor 10 may request the data transmission interface 12 to operate at a maximum operating frequency, so as to complete the required processing in time.
FIG. 2 shows a schematic diagram of a corresponding relationship between an operating status of a processor and a clock rate of a data transmission interface. For a single-core electronic system, since a required interface transmission bandwidth can be acquired in advance by the single-core electronic system when the single-core electronic system switches from one task to another, an interface transmission rate between the processor and a data storage device such as a hard disk may be directly determined according to requirements of the processor itself. More specifically, the processor in a single-core electronic system is capable of switching the clock rate of the data transmission interface according to its operating status.
To enhance operating speeds of electronic systems, certain electronic system manufacturers wish to replace the conventional single-core electronic systems with multi-core electronic systems. For a multi-core system, tasks executed by multiple processors in the multi-core system within a same period may vary. It is therefore an essential issue to provide a solution for determining a transmission rate of a data transmission interface under the situation that a same data transmission interface is to be shared by the multiple processors to communicate with a data storage device.